In the present day scenario where Digital VLSI Designs are trending towards SOC designs with increased complexity, the Design Verification job is visibly becoming more and more software oriented. Both Design and Verification Engineers need to possess strong hardware and software skills surrounding the hardware and software interface. Additionally, with verification testbenches and simulation models becoming more and more complex, software programming knowledge has become a must-have skill for any Verification Engineer.

A Design Verification Engineer should know at-least one programming language thoroughly (C/C++/SystemVerilog), should have strong scripting skills, working knowledge and familiarity with UNIX/Linux environments, and a good understanding of object oriented programming concepts. Due to these reasons, questions that test a candidate’s understanding of programming basics are part of almost all Verification job interviews. Ability to think and code algorithms, and model design behaviors forms a vital component of an interview.

Hardware Description Languages (HDL) are used to model behavior of digital logic circuits independently of any underlying implementation technology. VHDL and Verilog were the two popular HDLs used for digital logic design, and in the recent years SystemVerilog (which is a super set of Verilog) has become more widely adopted as it supports object oriented programming concepts and several other features which are very useful for implementing testbenches that are used to verify designs.

This course (practice tests) is therefore organized into six time bound test papers covering some of the most commonly asked interview questions (180+ questions) with their answers. Targeted topics include Basic Programming concepts, Object Oriented Programming concepts, UNIX, Linux, C, C++, PERL, Verilog, and SystemVerilog(Basics).

Disclaimer

Every effort has been made to make these practice tests as complete and as accurate as possible, but no warranty is implied. The authors shall have neither the liability nor the responsibility to any person or entity with respect to any loss or damages arising from the information contained in these practice tests or other resources accompanying these tests.

These practice tests are independent work of the authors and are not endorsed by their employers.